A Comparative Study of CMOS Transimpedance Amplifier (TIA)
Priya Singh1, Vandana Niranjan2, Ashwni Kumar3
1Priya Singh, Research Scholar, Indira Gandhi Delhi Technical University for Women, Kashmeri Gate, Delhi, India.
2Dr. Vandana Niranjan, Professor, Indira Gandhi Delhi Technical University for Women, Kashmeri Gate, Delhi, India.
3Prof. Ashwni Kumar, Professor, Indira Gandhi Delhi Technical University for Women, Kashmeri Gate, Delhi, India.
Manuscript received on 12 January 2023 | Revised Manuscript received on 25 February 2023 | Manuscript Accepted on 15 March 2023 | Manuscript published on 30 March 2023 | PP: 19-23 | Volume-3 Issue-1, March 2023. | Retrieval Number: 100.1/ijvlsid.A1215033123 | DOI: 10.54105/ijvlsid.A1215.033123
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© The Authors. Published by Lattice Science Publication (LSP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper a comparative study of different CMOS transimpedance amplifier has been presented. Standard device parameters of transimpedance amplifier such as gain, input refereed noise, power dissipation and group delay are studied and compared. Here the transimpedance amplifier is divided on the basis of its topology and device technology used and performance is summarized to get the overview. Most of the analysis taken are performed on 0.18 µm technology and some are implemented using 45nm, 0.13µm , 65nm , and 90nm.
Keywords: CMOS, Transimpedance, Amplifier (TIA), Technology
Scope of the Article: VLSI Circuits and Design