Low Power Embedded SoC Design
G. Sasikala1, G. Satya Krishna2
1Dr. G. Sasikala, Department of Electronics and Communication Engineering, Vel Tech Rangarajan Dr. Sagunthala R&D Institute of Science and Technology, Morai (Tamil Nadu), India.
2G. Satya Krishna, Department of Electronics and Communication Engineering, Vel Tech Rangarajan Dr. Sagunthala R&D Institute of Science and Technology, Morai (Tamil Nadu), India.
Manuscript received on 14 January 2023 | Revised Manuscript received on 27 January 2023 | Manuscript Accepted on 15 March 2023 | Manuscript published on 30 March 2023 | PP: 1-10 | Volume-3 Issue-1, March 2023. | Retrieval Number: 100.1/ijvlsid.A1216033123 | DOI: 10.54105/ijvlsid.A1216.033123
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© The Authors. Published by Lattice Science Publication (LSP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Now a days all embedded processors are manufactured in such a way that it may consume low power to provide longer life to the system using various low power techniques like clock gating, data gating, variable frequency mechanism, variable voltage mechanism and variable threshold techniques. In this paper these techniques are implemented using VHDL language in Vivado and results are compared to identify the better one among all possible ones. There are various characteristics compared here are power consumption, number of look up tables and number of flip flops consumed.
Keywords: VHDL, Clock Gating, Data Gating, Frequency Scaling.
Scope of the Article: VLSI Circuits and Design