Review of 6T SRAM for Embedded Memory Applications
Pradeep Singh Yadav1, Harsha Jain2
1Pradeep Singh Yadav, Shri Shankaracharya Technical Campus, Bhilai (Chhattisgarh), India.
2Harsha Jain, Shri Shankaracharya Technical Campus, Bhilai (Chhattisgarh), India.
Manuscript received on 02 March 2023 | Revised Manuscript received on 04 March 2023 | Manuscript Accepted on 15 March 2023 | Manuscript published on 30 March 2023 | PP: 24-30 | Volume-3 Issue-1, March 2023 | Retrieval Number: 100.1/ijvlsid.A1217033123 | DOI: 10.54105/ijvlsid.A1217.033123
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© The Authors. Published by Lattice Science Publication (LSP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Due to the substantial impact embedded Static Random Access Memory (SRAM)s have on the overall system and their relatively limited design, it is essential to manage embedded SRAM trade-offs strategically. SRAMs have power, performance and density trade-offs in general. In all applications, all three dimensions are necessary to some extent; accordingly, embedded SRAM design must incorporate the most crucial system-specific requirements when developing embedded SRAM. This paper discusses many SRAM factors, including Static Noise Margin (SNM), Read Access Time (RAT),Write Access Time (WAT), Read Stability and Write Ability, Power, Data Retention Voltage (DRV), and Process Control. All these factors are crucial when designing SRAM for embedded memory applications. There has also been a discussion of the parameter comparisons and the literature review of the current papers.
Keywords: Area, Memory Application, Latency, Power, SNM, SRAM
Scope of the Article: VLSI Circuits and Design