Design of Carry Select Adder using BEC and Common Boolean Logic 
Syed Mustafaa M1, Sathish M2, Nivedha S3, Mohammed Magribatul Noora A K4, Safrin Sifana5
1Syed Mustafaa M, Department of Electronics and Communications Engineering, Aalim Muhammed Salegh College of Engineering, Chennai, India.
2Sathish M, Department of Electronics and Communications Engineering, Aalim Muhammed Salegh College of Engineering, Chennai, India.
3Nivedha S, Department of Electronics and Communications Engineering, Aalim Muhammed Salegh College of Engineering, Chennai, India.
4Magribatul Noora A K, Department of Electronics and Communications Engineering, Aalim Muhammed Salegh College of Engineering, Chennai, India.
5Safrin Sifana T, Department of Electronics and Communications Engineering, Aalim Muhammed Salegh College of Engineering, Chennai, India.
Manuscript received on 03 December 2021 | Revised Manuscript received on 14 December 2021 | Manuscript Accepted on 15 March 2022 | Manuscript published on 30 March 2022 | PP: 5-9 | Volume-2 Issue-1, March 2022. | Retrieval Number: 100.1/ijvlsid.C1205031322 | DOI: 10.54105/ijvlsid.C1205.031322
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Abstract: Carry Select Adder (CSLA) is known to be the fastest adder among the conventional adder structure, which uses multiple narrow adders. CSLA has a great scope of reducing area, power consumption, speed and delay. From the structure of regular CSLA using RCA, it consumes large area and power. This proposed work uses a simple and dynamic Gate Level Implementation which reduces the area, delay, power and speed of the regular CSLA. Based on a modified CSLA using BEC the implementation of 8-b, 16-b, 32-b square root CSLA (SQRT CSLA) architecture have been developed. In order to reduce the area and power consumption in a great way we proposed a design using binary to excess 1 converter (BEC). This paper proposes an dynamic method which replaces a BEC using Common Boolean Logic.
Keywords: SQRT CSLA, BEC, CBL.
Scope of the Article: VLSI Circuits and Design